This application is based upon and claims the benefit of priority from the prior Japanese Patent Application No. 2000-296081, filed Sep. 28, 2000, the entire contents of which are incorporated herein by reference.
1. Field of the Invention
The present invention relates to a semiconductor memory device, and in particular, to a read register.
2. Description of the Related Art
A circuit configuration of a general high frequency clock synchronous memory is shown in FIG. 23. A memory circuit 1 is roughly composed of a memory core section 2 and the other interface I/F circuit.
The I/F circuit comprises: adjacent left and right shift register section 3 at the memory core section 2; left and right I/O circuits (input/output circuits) 4 disposed between the corresponding external signal lines; a DLL (Delayed Locked Loop) circuit 5; and a control logic 6.
The DLL circuit 5 is a circuit that synchronizes with an externally inputted write clock RXCLK, thereby generating a clock xe2x80x9crclkxe2x80x9d that controls internal write data, and generating a clock xe2x80x9ctclkxe2x80x9d that controls internal read data in response to an externally inputted readout clock TXCLK.
In addition, a control logic 6 is a circuit that logically computes a protocol inputted by an external command signal COMMAND, and generates a memory circuit control signal.
The left and right I/O circuits 4 each acquires serial write data DQ  less than 0:7 greater than  and DQ  less than 8:15 greater than  from an external input/output data line by using an internal write data control clock xe2x80x9crclkxe2x80x9d, and outputs internal serial write data eWrite and oWrite to be inputted to the left and right shift register section 3 that consists of a plurality of shift registers.
In addition, by using the internal read data control clock xe2x80x9ctclkxe2x80x9d, the internal serial read data eRead and oRead are acquired respectively from the left and right shift register section 3, and serial read data DQ  less than 0:7 greater than  and DQ  less than 8:15 greater than  are outputted respectively to the external input/output data lines.
The  less than 0:7 greater than  and  less than 8:15 greater than  used here denotes first-half 8DQ data and latter-half 8DQ data of 16DQ. The characters xe2x80x9cexe2x80x9d and xe2x80x9coxe2x80x9d assigned to Read and Write denotes even number (even) and odd number (odd) data.
The left and right shift register sections 3 each acquire the internal parallel read data RD  less than 0:7 greater than  respectively read out from the memory core section 2 by a control signal during readout operation. Then, these register sections each output the internal parallel write register WD  less than 0:7 greater than  respectively by a control signal during write operation, and then, writes it into the memory core section 2.
In this way, the internal parallel read data RD  less than 0:7 greater than  is converted into the internal serial read data xe2x80x9ceReadxe2x80x9d and xe2x80x9coReadxe2x80x9d during readout operation between the left and right I/O circuits 4 each and the memory core section 2. In addition, the internal serial write data xe2x80x9ceWritexe2x80x9d and xe2x80x9coWritexe2x80x9d are converted into the internal parallel write data WD  less than 0:7 greater than  during write operation.
The memory core section 2 is composed of a general DRAM circuit that consists of a row decoder, a column decoder, a memory cell array, a sense amplifier, a redundancy phase, and a DQ buffer.
As described above, in a layout configuration of a conventional high frequency clock synchronous memory, parallel read data read out from the memory core section 2 is converted into serial read data by the shift register 3, and the converted serial read data is delivered to the I/O circuit 4. FIG. 24 shows a path from the conversion to the delivery. Serial numbers 0 to 7 and 8 to 15 are assigned to the left and right I/O circuits 4 incorporated in a peripheral circuit section 7 enclosed by dotted line.
In the case where data is written into the memory core section 2, the serial write data inputted from the I/O circuit 4 is inputted to the shift register section 3. Then, the inputted write data is written into the memory core section 2 after converted into parallel write data at the shift register section 3.
In this way, a data flow in write operation can be obtained by reversing the data flow in readout operation. Thus, FIG. 24 shows a path of read data as an example of readout operation.
In FIG. 24, at the memory core sections 2 disposed at the top and bottom of the peripheral circuit section 7, the 8-bit regions each are assigned to the left memory core section 2, corresponding to each of the left 8-bit I/O circuits 4 having serial numbers 0 to 7 assigned thereto. Similarly, the 8-bit regions each are assigned to the right memory core section 2, corresponding to each of the right 8-bit I/O circuits 4 having serial numbers 8 to 15 assigned thereto. Namely, a 16-bit configured high frequency clock synchronous memory is entirely configured.
In this way, as is evident from the memory core section 2 in FIG. 24, the 8-bit regions (I/O) 0 (0:7) to (I/O) 15  less than 0:7 greater than  each are assigned to a cell array. When the high frequency clock synchronous memory is active, the above four memory core sections 2 are selected according to a combination of the upper left and lower right or a combination of the lower left and upper right by an address signal.
The read data read out in parallel from the memory core section 2 every 8 bits is converted into each items of 8-bit serial read data at the shift register section 3. Configurations of the shift register section are shown in FIGS. 25 and 26, and a disposition of the shift register section 3 relevant to the memory core section 2 and peripheral circuit section 7 is shown in FIG. 27.
As shown in FIGS. 25 and 26, the write register is composed of: an odd number write register that inputs 4-bit odd number serial write data xe2x80x9coWritexe2x80x9d, and outputs 4-bit odd number parallel data WD  less than 1, 3, 5, 7 greater than  ; and an even number write register that inputs 4-bit even number serial write data xe2x80x9ceWritexe2x80x9d, and outputs parallel write data WD  less than 0, 2, 4, 6 greater than .
In addition, the read register is composed of: an odd number read register that acquires 4-bit odd number parallel read data RD  less than 1, 3, 5, 7 greater than , and outputs 4-bit odd number parallel read data xe2x80x9coReadxe2x80x9d and an even number read register that acquires 4-bit even number parallel read data RD  less than 0, 2, 4, 6 greater than , and outputs 4-bit even number parallel data xe2x80x9ceReadxe2x80x9d.
In more detail, these write register and read register use both edges of the write and readout control clocks xe2x80x9crclkxe2x80x9d and xe2x80x9ctclkxe2x80x9d to transfer 8-bit data at a clock of 4 cycles.
In addition, the shift register section 3 that consists of a write register and a read register is collected into a block in units of bits that corresponds to each of the bits (I/O) 0 to (I/O) 7, and a set of shift register sections are configured in a form in which the blocks in units of 8 bits are stacked in a Y direction.
As shown in a pattern layout of FIG. 27, such two sets of shift register sections 3 corresponds to 8 bits are disposed at the center in the X direction of a chip. That is, two sets of shift register sections 3 that correspond to 16 I/O circuits 4 are disposed at the center in the X direction.
From the I/O circuits 4, eight internal serial write data lines for even number data xe2x80x9ceWritexe2x80x9d and eight internal serial write data lines for odd number data xe2x80x9coWritexe2x80x9d are corrected respectively to the corresponding 8 write registers for each bit. Thus, a total of 16 internal serial write data are connected to eight write registers through a peripheral circuit.
In addition, eight internal serial read data lines for even number xe2x80x9ceReadxe2x80x9d and eight internal serial read data lines for odd number data xe2x80x9coReadxe2x80x9d are connected respectively to the corresponding eight read registers for each bit. Thus, a total of 16 internal serial read data lines extend to the peripheral circuit section, and are connected to the I/O circuit 4 through the peripheral circuit section.
When the wire resistance from the corresponding read register for each bit to the peripheral circuit section is defined as Rs, the wire resistance Rs from the bit corresponding register that is the most distant from the peripheral circuit section is obtained to be maximal.
Because of this, in a shift register circuit that gives priority to write operation as shown in FIG. 26, a delay of a propagation time caused by an increase in wire length Rs of the read registers xe2x80x9ceReadxe2x80x9d and xe2x80x9coReadxe2x80x9d is problematic, and there is a possibility that an operational margin cannot be maintained.
An example of read operation will be described by way of timing waveforms shown in FIG. 28. When a read command signal COMMAND is inputted, 8-bit read data RD  less than 0:7 greater than  are outputted in parallel from one of the memory core sections 2 after a predetermined time.
The 8-bit parallel read data RD  less than 0:7 greater than  synchronizes with a rise of xe2x80x9ctclkxe2x80x9d that controls internal read data, and is converted into 4-bit serial read data xe2x80x9coReadxe2x80x9d that consists of odd numbers 1, 3, 5, and 7.
Similarly, the RD  less than 0:7 greater than  synchronizes with a fall of the xe2x80x9ctclkxe2x80x9d that controls internal read data, and is converted into 4-bit serial read data that consists of odd numbers 0, 2, 4, and 6 at the xe2x80x9cevenxe2x80x9d side of the read register.
By combining them, a total of 8-bit serial read data having numbers 0 to 7 assigned thereto are externally outputted via the I/O circuit 4.
In this way, 8-bit serial read data is outputted at a 4-cycle xe2x80x9ctclkxe2x80x9d. That is, xe2x80x9coReadxe2x80x9d and xe2x80x9ceReadxe2x80x9d of each of four bits can be outputted alternately by using rise and fall edges of xe2x80x9ctclkxe2x80x9d.
The read register of the shift register section in this conventional circuit is shown in FIG. 29.
The RD  less than 0:7 greater than  outputted from the memory core section 2 is acquired by a load signal, and the read data RD  less than 0, 2, 4, 6 greater than  at the xe2x80x9cevenxe2x80x9d side is transferred through Pipe  less than n greater than  while the xe2x80x9ctclkxe2x80x9d is defined as a reference, and xe2x80x9ceReadxe2x80x9d are sequentially outputted. Similarly, with respect to the read data at the xe2x80x9coddxe2x80x9d side as well, the RD  less than 1, 3, 5, 7 greater than  pass through Pipe  greater than n greater than  signal, and oRead are sequentially outputted while the xe2x80x9ctclkxe2x80x9d is defined as a reference.
In such a pipeline system for a read register that gives priority to write operation, a total of 16 internal pipeline read data lines for even number data xe2x80x9ceReadxe2x80x9d and odd number data xe2x80x9coReadxe2x80x9d for transferring read data are required in a Y direction. The read register is composed of a total of 32 wires, thus resulting in an increase in area.
This FF circuit is shown in FIG. 30 to FIG. 32. In FIG. 30, each of the RD  less than 6, 4, 2 greater than  at the xe2x80x9cevenxe2x80x9d side and each of the RD  less than 7, 5, 3 greater than  at the xe2x80x9coddxe2x80x9d side are acquired by the respective outFF circuits one by one signals, and are transferred to the adjacent pipe read data at one cycle of each of the fall and rise of xe2x80x9ctclkxe2x80x9d. FIGS. 31 and 32 each show an FF circuit at the final stage of xe2x80x9ceReadxe2x80x9d and xe2x80x9coReadxe2x80x9d, where final adjustment is made, xe2x80x9ceReadxe2x80x9d is outputted by an outFF1 circuit (FIG. 31) that outputs the data at the xe2x80x9cevenxe2x80x9d side at a fall of xe2x80x9ctclkxe2x80x9d, and xe2x80x9coReadxe2x80x9d is outputted by an outFF1 circuit (FIG. 32) that outputs the data at the xe2x80x9coddxe2x80x9d side at a fall of xe2x80x9ctclkxe2x80x9d.
Read operation at this time will be described by way of a timing waveform chart shown in FIG. 33. A read command signal COMMAND is inputted, and 4-bit read data RD  less than 0:3 greater than  is outputted in parallel to the xe2x80x9cevenxe2x80x9d side from one of the memory core section after a predetermined time.
The 4-bit parallel read data RD  less than 0:3 greater than  at the xe2x80x9cevenxe2x80x9d side acquires all data by a load signal, and then, transfers pipe read data to the adjacent outFF circuit by an outFF circuit while the xe2x80x9ctclkxe2x80x9d is defined as a reference.
In this way, xe2x80x9ceReadxe2x80x9d data is outputted for each cycle. In an outFF circuit that outputs Pipe 3 after data has been delivered, even after read data of RD  less than 3 greater than  has been delivered, the FF circuit continuously operates while xe2x80x9ctclkxe2x80x9d is defined as a reference, and an unnecessary 3-cycle operation is made. Similarly, in an outFF circuit that outputs Pipe 2 as well or in an outFF circuit that outputs 2-cycle Pipe 1 as well, an unnecessary one-cycle operation is made. Similar operation is made at the xe2x80x9coddxe2x80x9d side as well.
Because of this, the FF circuit operates during an operation other than necessary read data transfer, and thus, the corresponding power is excessively applied.
In addition, FF circuits with the xe2x80x9ctclkxe2x80x9d being defined as a reference are incorporated for each bit one by one, whereby eight FF circuits are incorporated in each I/O. Thus, 128 FF circuits operate at the same time during one read register circuit operation, and more power is excessively applied.
Further, in such a pipeline circuit, read data are sequentially transferred by using Pipe  greater than n greater than  while the xe2x80x9ctclkxe2x80x9d is defined as a reference. Thus, only data transfer in predetermined sequence can be performed, eliminating the flexibility for data readout.
A semiconductor memory device according to an embodiment of the present invention comprises: a memory cell array including a plurality of memory cells; a first latch circuit group including a plurality of latch circuits, the first latch circuit group latching n/2 of n-bit read data outputted from the memory cell array, and sequentially outputting the latched n/2 bit read data in response to sequentially shifted read control signals (xe2x80x9cnxe2x80x9d denotes a natural number); a first output circuit, the first output circuit sequentially outputting the n/2 bit read data sequentially outputted from the first latch circuit group as n/2 bit serial read data in synchronism with a clock signal; a second latch circuit group including a plurality of latch circuits, the second latch circuit group latching the remaining n/2 of n-bit read data outputted from the memory cell array, and sequentially outputting the remaining latched n/2 bit read data in response to the sequentially shifted read control signal; and a second output circuit, the second output circuit sequentially outputting the remaining n/2 bit read data sequentially outputted from the second latch circuit group as the remaining n/2 bit serial read data in synchronism with the clock signal.